Multistable circuit



Sept. 8, 1959 R. A. HENLE MULTISTABLE CIRCUIT Sept 8, 1959 R. A. HENLE 2,903,604

MULTISTABLE CIRCUIT Filed Jan. 3, 1955 8 Sheets-Sheet 2 Sept. 8, 1959 R. A. HENLE MULTISTABLE CIRCUITv 8 Sheets-Sheet 3 Filed Jan. 3, 1955 INVENToRs ROBERT A. HENLE ATTO EY Sept. 8, 1959 R. A. HENLE 2,903,604

MULTISTABLE CIRCUIT Filed Jan. 3, 1955 8 Sheets-Sheet 4 FIG.8

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INVENTORS ROBERT A. HENLE Sept 8, 1959 R. A. HENLE 2,903,604

MULTISTABLE CIRCUIT Filed Jan. 5, 1955 8 Sheets-Sheet 8 E /195 g2bN N 2 I I l l l e 185 I l l I l :/188 1ees l l l I L J Vc O 1960 FIG. 1,8

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i f INVENToRs ROBERT A. HENLE E BY ATTORNE United States Patent Patented Sept. 8, 1959 ice MULTISTABLE CIRCUIT Robert A. Henle, Hyde Park, N.Y., assignor to International Business Machines Corporation, New York, N.Y., a corporation of New York Application January 3, 1955, Serial No. 479,413 E19 Claims. (Cl. 307-885) This invention relates to electrical circuits having a multiplicity, i.e., more than two, of stable output states.

There has come into widespread use in recent years a type of electric circuit known as a bistable circuit, havlng two distinct stable output states. Such circuits are shiftable back and forth between their output states in response to successive input signals, which may, for example, be square wave signals. Such circuits have a large number of uses, particularly in the eld of high speed electrical computers. For example, they are used as triggers and also as counters. When a bistable circuit is used as a counter it is necessarily limited to counting in accordance with the binary system, in which each numerical order includes only two digits. The two digits of an order are then represented by the two stable output states of the bistable circuit. One bistable circuit must be provided for each binary order in a counter of that type. Where large numbers are involved, the number of binary orders is likewise large, and the circuits required become large and complex.

Circuits constructed in accordance with the present invention have more than twostable output states. There is theoretically no limit as to the number of stable output states which may be designed into a single stage circuit. Practically, however, in order that the several stable output states may remain distinct, the number of such output states is limited by the accuracy with which the resistances of the various impedance elements may .be determined. It is quite easy, in accordance with the present invention, to provide a circuit having ten stable output states, which is serviceable as a decimal counter.

The multistable circuits of the present invention use a novel impedance network identified herein by the generic term step function impedance means. By this term is meant an impedance means whose volt-ampere characteristic has a form approximating that of the profile of a iiight of steps or stairs.

An object of the present invention is to provide a multistable circuit.

Another object of the invention is to provide a novel counter utilizing a multistable circuit.

Another Objectis to provide step 'function impedance means which may be used to load a translating device.

The foregoing and other objects of the invention are attained in the circuits described herein by providing a translating device, typically a transistor, with step function impedance means connected to it 'as a load. The output of that device is connected through suitable feedback means, which may include another translating device, to the input of the iirst device. Such a circuit .has a multiplicity of stable output states, the number of such output states depending upon the number of steps provided by the step function impedance means. A multistable circuit of the type just described is readily adaptable for use as a counter, by providing an input gate circuit which switches the multi-stable circuit from one of its states to the next in response to an input pulse. A11 output gate is provided for producing an output signal when the multi-stable circuit has counted its full range of states. For example, in the case of a decimal counter, an output gate is provided to produce an output pulse when the multistable circuit reaches its tenth stable state. Either count-up or count-down input gates may be provided, with corresponding high end or low end output gates. Set and reset means may be provided as desired for establishing the multistable circuit in one or the other of its two end states.

The step function impedance means illustrated comprises a network including a plurality of branches. A typical branch consists of first and second oppositely poled diodes connected to a common junction, said first diode having its opposite terminal connected to a biasing battery. The second diode has its opposite terminal connected to the output terminal of a translating device, typically the collector of atransistor. The common junction is connected through a load resistor to a load supply battery. With this arrangement, whenever the potential at the collector is below the potential of the biasing battery, then the second diode is reversely biased and no current ows from the collector through the load resistor. As the potential of the collector increases, it eventually becomes greater than that of the biasing battery, whereupon current ows from the collector through the load resistor, which is thereby added to the load on the transistor. By connecting several such branches to ythe collector, with diiferent biasing potentials in each branch, a load impedance is constructed whose effective impedance varies in steps as the collector potential changes.

Other objects and advantages of the invention will become apparent from a `consideration of the following specification and claims, taken together with the accompanying drawings.

In the drawings:

Fig. l is a wiring diagram of a counter including a. multistable circuit embodying the invention;

Fig. 2 is a wiring diagram of a simplified circuit similar to that employed in Fig. l, illustrating the principles on which the circuit of Fig. l operates;

Fig. 3 is a graphical illustration ofthe collector voltampere characteristics of one of the transistors in the circuit of Fig. l, with a step function load line superimposed thereon;

Fig. 4 is a wiring `diagram of a complete decimal counter circuit incorporating a multistable circuit, and also including a count-up input, a nine count output and reset means;

Fig. 5 is a fragmentary wiring diagram showing an alternative zero reset circuit which may be used in place of the manual reset circuit of Fig. 4;

Fig. 6 is a fragmentary wiring diagram showing an alternative form of count-up input gate whichk may be used in place of the input gate of Fig. 4.

Fig. 7 is a wiring diagram showing still another form of input gate which may be used with the circuit of Fig. l or the circuit of Fig. 4;

Fig. 8 is a fragmentary wiring diagram showing a count-down input gate, signal generator and reset gate which may be used with the circuit of Fig. 4;

Fig. 9 is a fragmentary wiring diagram showing a downcount output gate which may be used with the circuit of Fig. 4;

Fig. l0 is a fragmentary wiring diagram showing an alternative reset gate which may be used with the circuit of Fig. 4;

Fig. l1 is a wiring diagram of a modilied form of counter circuit embodying the invention;

Fig. l2 is a fragmentary wiring diagram of still another form of counter circuit embodying the invention;

Fig. 13 is a graphical illustration corresponding generally to Fig. 3, but relating to the circuit of Fig. l2;

Fig. 14 is a wiring diagram of a modified form of counter circuit embodying the invention, and operated from a single source of electrical energy;

Fig. is a wiring diagram of a multistable circuit embodying the invention, and employing vacuum tubes instead of transistors;

Fig. 16 is a graphical illustration of the operating characteristics of one of the vacuum tubes of Fig. l5, with a step function load line superimposed thereon;

Fig. 17 is a wiring diagram of a portion of a counter similar to that of Fig. 1, but employing a modified form of step function impedance means;

Fig. 18 is a graphical illustration similar to Fig. 3, but relating to the circuit of Fig. 17; and

Fig. 19 is a wiring diagram of a modiied form of multistable circuit employing a point contact transistor.

FIGS. 1 TO 3 Figure 1 includes a multistable circuit employing PNP junction transistors 1 and 2, having emitter electrodes 1e and 2e, base electrodes 1b and 2b, and collector electrodes 1c and 2c. Associated with this multistable circuit is an input gate 45 including a PNP junction transistor 3 having an emitter electrode 3e, a base electrode 3b, and a collector electrode 3c.

The transistor 1 is connected in a grounded base amplifier stage. Its base 1b is connected to ground and its collector 1c is connected to a step function impedance load, generally indicated by the reference numeral 4. A feedback is provided between collector 1c and emitter 1e, this feedback including transistor 2 which is connected in a grounded collector amplifier stage. Base 2b is directly connected to collector 1c. The load on transistor 2 is connected to its emitter 2e and comprises two resistors 5 and 6 connected in series with a load battery 7. A biasing battery 8 is connected between collector 2C and ground. The feedback mentioned above may be traced from the common junction 9 between the resistors 5 and 6 through wire 10 to the emitter 1e of transistor 1.

The step function impedance load 4 is an electrical network including tive branches connected between collector 1c and ground. One of these branches may be traced from collector 1c through a diode 11 and a battery 12 to ground. A second of these branches may be traced through a load resistor 13 and a battery 14 to ground. A third of these branches extends through oppositely poled diodes 15 and 16, and battery 17 to ground, and includes a load resistor 23 connected between the common junction 24 of diodes 1S and 16 and the negative terminal of battery 14. The fourth of these branches extends through oppositely poled diodes 18 and 19 and a battery 20 to ground, and includes a load resistor 25 connected between the common junction a of diodes 18 and 19 and the negative terminal of battery 14. The lifth branch may be traced through diode 21 and a battery 22 to ground.

The batteries 12, 14E., 17, 2t) and 22 are all connected with their positive terminals grounded. Battery 14 has a much greater potential than any of the others, for example, 309 volts. Batteries 12, 17, 241 and 22 have potentials decreasing from one to the other, in the order named. For example, their potentials may respectively be l0, 7.5, 5 and 2.5 volts.

The input gate 4S includes, in addition to transistor 3, three resistors 26, 27 and 28 connected in series, the series group being connected in parallel with load resistors 5 and 6. Emitter 3e of transistor 3 is connected to the common junction 29 between resistors 26 and 27. Base 3b is connected through a resistor 30 to the common junction 31 between resistors 27 and 28. A capacitor 32 is connected between junction 2 and ground. Base 3b is connected through a capacitor 33 to a square wave input signal generator schematically indicated at 34.

(jenerl ator 34 may have, for example, a no-signal potential of O volts and a signal potential of 2.5 volts. Collector 3c is connected through a wire 3S to base 2b.

Emitter 2e is connected to an output gate 48 compris ing a diode 36, a resistor 37 and a battery 38 in series, the opposite terminal of battery 38 being connected to ground. The terminal of resistor 37 nearest diode 36 is connected to an output terminal 39. Another output terminal 40 is grounded. The circuit of Fig. l produces between the output terminals 39 and 40 output signals illusytrated within a frame 41 as being square waves varying between a no-signal potential of 4 Volts and a signal potential of l volt.

OPERATION OF FIG. l

ln order that the operation of the circuit of Fig. l may be readily understood, it is desirable first to consider the circuit of Fig. 2, which comprises the circuit fo Fig. l stripped `down to its essentials, and employing a conventional load in place of the step function impedance load 4 of Fig. l. Those circuit elements of Fig. l which appear in the stripped down circuit of Fig. 2 have been given the same reference numerals, and will not be further described.

The circuit of Fig. 2 is a two stage transistor amplifier circuit, the transistor 1 being connected with its base grounded and the transistor 2 with its collector nominally grounded. The output of the second stage is fed back to the input of the first stage. Output terminals 42 and 43 are respectively connected to the emitter 2e and to ground.

Consider now the factors which determine whether the circuit of Fig. 2 is to be stable or unstable. A grounded 'base transistor amplifier stage, such as that including the transistor 1, has a current amplification substantially equal to l.

For each diferential increment of current through collector 1c, there is a corresponding increment of current through base 2b. Similarly, for each differential increment of current through base 2b, there is a corresponding increment of current through emitter 2e. Furthermore, for each differential increment of current through emitter 2e, there is a corresponding differential increment of current fed back through wire 1G to emitter 1e. Taking all these relationships together, it may be stated that for each differential increment of current fiowing through collector 1c, there is a corresponding diferential increment of current yfed back through wire 10.

Let Isl represent the current W through collector 1c Let Iel represent the current o-W through emitter 1e Let That is to say, B represents the diiferential ratio between the current fed back to emitter 1e and the current through collector 1c. Since the current amp-lication factor of the stage including transistor 1 is substantially equal to l, it may be seen that if B is greater than l, then an increasing collector current produces a more rapidly increasing emitter current, which in turn produces a further increase in collector current. Hence, the circuit is unstable. On the other hand, if B is less than l, then an increase in the collector current .produces a smaller increase in the emitter current and the circuit is stable.

Let us now determine which circuit parameters affect B', so that the circuit may be designed for stability or instability, as required.

Let

E7 be the potential of the positive terminal of battery 7, R6 be the resistance of resistor 6 E82 be the potential of emitter 2e R5 be the resistance of resistor 5 E8 be the potential of the negative terminal of battery 8 R44 be the resistance of resistor 44.

It may be assumed, without substantial error, that the emitter-to-base impedances in the transistors 1 and 2 are negligible, and that the'base currents are negligible.

The current flowing into emitter 1e is the difference between the current flowing through resistor 6 and the current owing through resistor 5. 'Ihis may be expressed by the following equation (assuming junction -9 to be at 0 Volts):

R. R5 (l) Diterentiating 1) It is assumed that the current through base 2b is negligible. This assumption is justified since the input resistance of the 4grounded collector stage is approximately which is much greater than R14. Ditferentating (3), we get dEe2=R44dIc1 Substituting (4) in (2), we get R dIelzozl-cl) which may be rewritten as d1., 2 itl-,1 R5 BI (6) From Equation 6, it follows that if the resistance of resistor 44 is greater than resistor 5, (B greater than 1), then the circuit will be unstable, and if the resistance of resistor 44 is less than the resistance of resistor 5, (B less than 1), then the circuit will be stable. Applying this equation to the circuit of Fig. l, that circuit is unstable when the impedance of the stepr function impedance means 4 is greater than that of resistor 5, and is stable when that impedance is less than the impedance of resistor 5.

Consider the load line 4a of Fig. 3, which is there superimposed upon a set of collector volt ampere characteristics, taken for constant emitter current,ffor the transistor 1 of Figs. 1 and 2, in the grounded base connection shown. The load line 4a has a step formation consisting of regions A, C, E, G where the resistance of the load Vis low, connected by regions B, D and F, where the resistance of the load is high. By choosing the resistance of resistor 5 properly, between these low and high values, the circuit of Fig. 2 may be made stable in the low resistance regions A, C, E and G and unstable in the high resistance regions B, D and F.

The step function impedance means 4 of Fig. 1 establishes a load on the transistor 1 which follows the line 4a of Fig. 3.

Referring to Fig. 3, it may be seen that section A of load line 4a intersects the Vc `axis at E12, which (neglecting the forward drop across diode 11) is the potential of the negative terminal of battery 12. Section C of load line 4a, if extended along the dotted line until it intersected the Vc axis, would intersect it at E17, which is the potential of the negative terminal of battery 17 in Fig. l. Similarly, section E extended would intersect the .same axis at E20 and section G extended at E22.

The operation of the circuit of Fig. 1 will now be considered as the potential fat collector 1c 'varies from a value of E12 to E22, With reference to Fig. 3.

Battery 12 and' diode 11 form a clamp for limiting the negative swing of the potential of collector 1c. If collector 1c tends to go to a more negative potential, then diode 11 becomes biased forwardly, and battery 12 is effective to clamp the potential of collector 1c at E12.

The load on collector 1c is then only the low forward impedance of the diode 11, as indicated by the nearly vertical slope of section A of the load line 4a.

Consider the conditions ynow existing in the branch circuit including diodes 15 and 16, battery 17 and resistor 23. Referring to diode 16, it may be seen that its cathode is connected through resistor 23 to the negative terminal of battery 14, which isl considerably more negative than the negative terminal of battery 17. Diode 16 is therefore forwardly biased, and junction 24 is at substantially the potential of the negative terminal of battery 17. Collector 1c is at a potential substantially more negative than the negative potential of battery 17. Diode 15 is therefore reversely biased, and no current ows through it from collector 1c.

As the potential of collector 1c increases from the value E12, diode 11 becomes biased in the reverse direction. This change takes place quickly, during a change in the collector potential from E12 to a value equal to the sum of E12 and the forward potential drop across diode 11, during which transistor 1 is operating in the stable region A of Fig. 3. As the collector potential continues to increase, the diode 11 becomes reverse biased, and it is eifectively removed as a load on collector 1c. This takes place at collector potential EA, and lthe load on collector 1c thereupon becomes the impedance of resistor 13, which is very high as compared to the forward impedance of diode 11. This high impedance is illustrated by the nearly horizontal slope of section B of the load line 4a.

The section B defines an unstable region through which the circuit quickly passes. If the collector potential is increasing, it passes quickly from EA to E17. At that potential, diode 15 becomes forwardly biased, and starts to conduct current.

For low values of current flow through diode 15, the junction 24 may be considered as a point of xed potential. Within ithat range of low current values, an increase in current flow through diode 15 is accompanied by a decrease in current flow through diode 16. Resistor 23 and battery 14 then operate as a substantially constant current drain.

That range of low current values corresponds to the stable region C of Fig. 3, and to a range of collector potentials between E17 and Ec. The eective incremental load on collector 1c in that region is only the forward impedance of diode 15, which is represented in Fig. 3 by the nearly Vertical slope of section C.

As the potential of collector 1c increases to Ec, the current flow through diode 15 equals that originally supplied through diode 16, and, when the collector potential increases beyond that value, resistor 23 is added as a load to collector 1c, in parallel with resistor 13.

The impedance load on the collector 1c, is then relatively high, as shown by the nearly horizontal slope of the section D of load line 4a. (Note that the slope of section D is slightly greater than the slope of section B, because of the reduction of the load impedance by the addition of resistor 23 in parallel with resistor 13. This difference in slope is exaggerated in the drawing.) When the collector potential reaches the value E20, the circuit enters another stable region E, where the only effective load is the forward impedance of diode 18. When the collector potential reaches the value EE, resistor 25 is added as a load in parallel with resistors 13 and 23 and the circuit operates in ythe unstable region F. When the collector potential reaches the Value E22, the diode 21 is biased forwardly, and it effectively shunts the other load 7 impedances and becomes the only effective load impedance on collector 1c so that the circuit operates in the stable region G, with the collector potential clamped at the value E22.

The operating potentials of the various steps in a multistable circuit will normally be selected near the center of the stable regions A, C, E or G. It may be assumed, for the purposes of the present description, that these potentials are equally spaced. These potentials will hereinafter be identified as EA, EC, EE and EG.

in the circuit of Fig. l, the input gate 45, including the transistor 3, operates to shift the multistable circuit from one stable state to the next upon receipt of a succession of input signals. The impedances of the resistors 26, 27 and 2S are selected so that the potential of junction 29 is always one step more positive than the potential of emitter 2e, which is substantially the same as the potential of base 2b, and hence of collector 1c. For example, if base 2b is at EA, then junction 29 is at EC. At the same time, junction 3l is substantially one volt more positive than junction 29. Since junction 31 is connected to the base 3b, and junction 29 is connected to emitter 3e, the base is more positive than the emitter, and the transistor 3 is cut off. Upon the receipt of a negative input signal of 2.5 volts, through capacitor 33 to base 3b, the small (l volt) positive bias of base 3b is overcome, transistor 3 becomes conductive, and the potential at emitter 3e is conducted through wire 35 to base 2b and collector 1c. Base 2b and collector 1c are thereby shifted suddenly one potential step in a positive sense, for example, from EA to EC. This change in potential also appears at emitter 2e, with a resultant decreased current iiow through resistor 5. Battery 7 produces a substantially constant current flow through resistor 6 (junction 9 being always substantially at ground potential), which current flow divides between emitters 1e and 2e. Consequently, when the current flow through resistor decreases, there is a corresponding increase of current flow through emitter 1e, so that the collector 1c becomes stably established at a new potential, i.e., where current line 18:3 crosses load line 4a.

rThe current iiow through emitter 1e when collector 1c (and hence emitter 2e) is at its lowest potential is determined by the resistances of resistors 5 and 6 and the potential of battery 7. These values should be chosen so that the constant emitter current line in Fig. 3 for that value of emitter current intersects the load line 4a near the middle of section A, eg., as the line Ie=l ma. does in Fig. 3. The voltage steps in the load line are determined by the several potentials of batteries 14, 17, 20 and Z2, and the current steps are determined by the relationship:

Digi-EL@ c urrent step The time constant of the input circuit of transistor 3 is lower than the time constant of the voltage divider including resistors 26, 27 and 28, so that the negative input signal disappears by the time the junctions 29 and 3i are established at their new potential values. Consequently, transistor 3 is cut oft between successive input signals.

The output gate, including diode 36, resistor 37 and battery 3S is set to produce an output signal whenever the collector ic reaches its highest stable output potential, in this case EG. The battery 3S is eiective when the emitter 2e is below that ouput potential to bias the diode 36 reversely so that output terminal 39 is substantially at the negative potential of battery 38, which may be, for example -4 volts. When the emitter 2e reaches the potential of the highest stable state, then diode 36 becomes biased positively and the potential at output terminal 39 suddenly increases to that more positive value, which may be -1 volt,

8 PIG. 4

The circuit illustrated in this gure is based on the circuit of Fig. l, but it has'beenmodified to provide a cornplete decimal counter. VThose circuit elements in Fig. 4 which are the same. .as their counterparts in Fig. 1 have been given .the same reference characters.

The output gate 48 of Fig. 4 produces a signal on the tenth input signal. An automatic reset gate 50 is provided through which the circuit is reset to Zero count each time a ten count output signal is produced.

The step function impedance network which functions as a load on transistor 1 is modified in the circuit of Fig. 4 by providing eight diode controlled load resistors in place of the two such resistors in Fig. l, so that the circuit has a total of-ten stable output states. Also, an arrangement is provided for supplying bias potentials for the diode controlled branches from a single battery 53, which also serves as a biasing battery for collector 2c Vof transistor 2.

Battery 53 supplies electrical energy to a voltage divider including ten resistors in series, numbered consecutively from 54 to 64.

Ten branch circuits are connected between collector 1c and ten points spaced along the voltage divider. The rst of these branch circuits includes a diode 65 connected between collector 1c and the common junction of resistors 54 and 55 in the voltage divider, and a resistor 66 connected between collector 1c and the negative terminal of battery 14. Each of the next eight branch. circuits includes oppositely poled diodes 67 and 68 connected between collector 1c and appropriate points along the voltage divider. Each pair of diodes 6,7 and 68 has a common terminal 69 connected through a resistor 76 to the negative terminal of battery 14. The tenth branch circuit includes a diode 7l, connected to the common junction of resistors 63 and 64 of the Voltage divider.

Diode 65 is a clamping diode establishing the most negative potential of collector 1c and diode 7l establishes the most positive potential of collector itc. Load resistor 66 corresponds generally to resistor i3 of Fig. l.

A manual zero reset gate 87 is connected to wire 10, and includes a capacitor 78, a diode 79, a battery and a switch ll. When switch 31 is closed, the emitter 1e is set at a negative potential, and transistor 1 is completely cut oft", so that its collector 1c swings to, the negative potential established by the clamping diode 6,5.

While the gate operated by switch 8i has been described as a manual zero reset gate, and switch 81 has been described as a manually operable switch,'it should be obvious to those skilled in the art that any mechanically equiv-alent automatic means may be substituted for the switch 81 to actuate the gate as required, in order to establish the counter at its zero count condition.

The signal generator 34 is shown in Fig. 4 as includ ing a transistor 46 having an emitter electrode 46e, a base electrode 46h and a collector electrode 46c. Base 46h is connected to groundthrough a resistor 47 and is connected through a capacitor 49 to a signal input terminal 51. Collector 46c is connected to ground through a battery 72. Emitter 46e is connected through a load fresistor 74 and a battery 75 to ground. Emitter 46e is connected through a resistor 76 and a wire 77 to capacitor 33 and thence to the base 3b of emitter 3e. The stage including transistor 46 is an emitter-follower stage of the type described in the copending application of George D. Bruce, et al. #459,382, tiled September 30, 1954. The emitter-follower circuit reproduces the input signals with substantially greater current and with lower output impedance.

The automatic reset gate 5,0 includes a diode 261 having its cathode connected to wire 77, and a resistor ZQZ connected between the anode .of diode 201 and the emitter 2e of transistor 2. rifhe anode of diode Zlii is also connected through `a capacitor 293 to the lemitter le of transistor 1.

9 oPERArroN oF FIG. 4

'Each input pulse receivedthrough the count-up input -gate 45'switches the transistorl' from one stable output condition to the stable output condition having the next higher potential. A series of nine input pulses at the gate 45 isV required to shift the circuit'from itslowest or zero counting level to its highest or nine counting level. When the potential at collector 1c reaches the nine counting level, an output signal is produced at the nine count output gate 48.

The circuit advancesup one step, i.e., the potential of collector 1c and hence of emitter 2e changes one step in a positive direction, in response to each negative going input pulse received at input terminal 51. The positive going edge of the pulse will not aifect the circuit, so that either peaked pulses as illustrated graphically in the drawing or square wave pulses may be used. After the ninth input pulse, the potential of emitter 2e is increased to a point where diode 201 is forwardly biased. The tenth input pulse, being repeated by the emitter-follower including the transistor 46, transmits a negative potential through diode 201 and capacitor 203 to emitter 1e, pulling the emitter 1e negative and cutting olf the transistor 1, so .that collector 1c is reset to its most negative potential.

FIG. 5

This figure illustrates a zero reset gate which may be used in place of the zero reset gate 87 of Fig. 4. This gate is connected to wire and consists simply of a switch 204 and a battery 205 having its positive terminal grounded and its negative terminal connected to switch 204.

When switch 204 is closed, emitter 1e is negatively biased and transistor 1 is cut off, so that the emitter 1c is switched to its zero count condition.

FIG. 6

This figure illustrates a simplied signal input circuit which may be used in place of the input gate 45 of Fig.l 1 or Fig.y 4. This input gate includes aresistor 83 and a parallel diode 84 having its cathode connected to wire 73 and thence to collector 1c. The anode of diode 84 is connected through a capacitor 85 to ground. The anode of diode 84 is also connected through a capacitor 86, and a manual switch 88 to the positive terminal of a battery 89, whose negative terminal is grounded.

Closing of switch 88 sends a positive impulse through diodev 84 to collector 1c. If this positive impulse is properly proportioned with respect to the voltage steps in the multistable network, each voltage impulse will step the network up from one step to the next higher positive step. It should readily be understood that the manual switch 88 may be replaced by any other equivalent mechy 10 flowing through resistor 208 to emitter 1e may be expressed as T In=lb e-RzusCaio Where:

R200 is the resistance of resistor 208, and

C210 is the capacitance of capacitor 210, and

T represents the time after the application of the input potential Ein.

It is desired to have the collector current I0 produced in response to an input current lin equal to the sum of the step current for the step function network plus the charging current required for capacitor 207 (as in the case of Fig. l, it is assumed that the emitter-to-base impedances of the transistors 1 and 2 are negligible, and that the base currents are negligible. Consequently, the current flow through resistor 206 may be neglected except for the charging current for capacitor 207). Expressing this desired relationship mathematically,

anism for completing the circuit between battery 89 and y capacitor 86.

FIG. 7

This figure illustrates a considerably more complex unit input gate arrangement which may be applied either to the circuit of Fig. l or the circuit of Fig. 4. Those elements in Fig. 4 which corresponds to elements in Fig. l have been given the same reference numerals. The transistor 3 of Fig. l and its related circuit elements are not used inthe circuit of Fig. 7. A resistor 206 is connected Y Where Es is one potential step of the step function network, RX is one impedance step of that network, R200 is the resistance of resistor 206 and C207 is the capacitance of capacitor 207. The rst term on the right-hand side of this equation is the step current and the second term is the charging current for capacitor 207.

The potential Efb at the emitter 2e (as in Fig. 1, it is assumed that junction 9 is constantly at ground potential) may be expressed as Where E is the potential at collector 1c before the triggering current impulse is received.

Balancing the currents at junction 9, it may be stated that E1 Erb lfb-Ra R5 10) where lfb is the current through wire 10.

Substituting Equation 9 in Equation 10, we get T E E Es fb=RZ|g+Rh5 1*@ RMON) (11) subtracting from the above equation for the collector current, the current required to charge capacitor 207 (see Equation 8 above), we get the current IL delivered to the step function network 4.

11 Now, if the circuit constants are proportioned so that then, substituting Equation 15 in Equation 14, we get The current delivered to the load before the application of the input pulse Em was E E ILR6+R5 R208 C210:R206 C207 (18) and also Ein l 1 :E5 19 R208 RRM i Equations 18 and 19 can be readily met by properly proportioning the several resistors and capacitors involved.

FIG. 8

This iigure illustrates a down-count input gate 213, which may be used in place of the up-count input gate 45 of Figs. l and 4.

The gate 213 includes an NPN junction transistor 214 having an emitter electrode 214e, a collector electrode 214e, and a base electrode 214b. Three resistors 2-15, 216 and 217, are connected in series with one another. The lower terminal of resistor 2 15, as it appears in Fig. 8, is connected to emitter 2e. The upper terminal of resistor 217 is connected to the negative terminal of a battery 218 whose positive terminal is grounded. Emitter 214e is Connected to the common junction 219 between resistors 215 and 216. Base 214b is connected through a resistor 220 to the common junction 221 between resistors 216 and 217. Base 214b is also connected through a capacitor 222 and the resistor 223 to the emitter 224e of an NPN junction transistor 224. Transistor 224 has a collector electrode 224C and a base electrode 224i). Collector 224C is connected through a collector biasing battery 225 and a circuit biasing battery 229 to ground. Base electrode 224k is connected through a resistor 226 and battery 229 to ground, and through a capacitor 227 to an input terminal 228. Emitter 224e is connected through a resistor 229, a battery 230 and battery 22951 to ground. The transistor 224 is connected in an emitter follower circuit generally similar to the emitter-follower circuit in Fig. 4 which includes the transistor 46. Emitter 224e is connected through resistor 223, a diode 231 and a resistor 232 to the emitter 2e of transistor 2. The common junction of resistor 232 and diode 231 is connected through a capacitor 233 and an amplifier 23351 to the collector 1c of transistor 1.

Positive going signals are received at terminal 228 and are repeated with current amplification by the emitterfollower circuit including transistor 224. The direct p0- tential level at emitter 224e is established by battery 229 at a value suiiiciently negative so that diode 231 is biased reversely until the potential of emitter 2e reaches its next to lowest step. The input signals are effective at transistor 214 to step down the potential of collector 1c by one voltage step. When the emitter 2e reaches the next to the lowest step, its potential is suiciently negative so that the diode 231 is then biased forwardly. Then when the neXt impulse is received at terminal 228, it is transmitted through diode 231, capacitor 233 and amplifier 23361 to collector 1c. Amplifier 23311 raises the signal potential suiiiciently so that it is eifective to swing the collector to its most positive potential, back to its highest or nine counting step, ready for further reduction` inthe registered count by successive impulses .at input terminal 228.

FIG. 9

This iigure illustrates a zero countoutput gate, which may be connected to emitter 2e. This gate includes a diode 234, a resistor 235 and a battery 236. One output terminal 237 is connected to the common junction of diode 234 and resistor 235. Another output terminal 238 is connected to ground. As long as the emitter 2e is above the potential of its lowest step, the diode 2-34 is biased reversely, and the output terminal 237 is at the potential of the negative terminal of battery 236. When emitter 2e reaches its lowest output potential then diode 234 is biased forwardly, and output terminal 237 remains at the potential of that lowest step. Consequently, an output signal is produced only when the count reaches its lowest step.

If the circuits of Figs. 8 and 9 are substituted respectively for the input gate 45 and the output gate 48 of Fig. 4, then the decimal counter circuit of that iigure is adapted for counting down or subtractingin response to each input signal, rather than counting up as inthe circuit of Fig. 4. The substitution of these circuits of Figs. 8 and 9 in the input and output gates of Fig. 4 may be accomplished by suitable automatic or manual switching mechanism, so that a single multi-stable circuit may be used for both up and down counts.

FIG. 10

This figure illustrates an alternative arrangement for resetting the decimal counter to its nine count step. This circuit consists simply of a switch 239 connected between collector 1c and ground. When` the switch 239 is closed, collector 1c is grounded, and the circuit is established on its nine count step. Suitable automatic mechanism may be used for operating switch 239 or equivalent electrical mechanism for grounding the col lector 1c may be substituted. For example, such electrical mechanism may respond to the output signal through terminal 237 in Fig. 9.

FIG. 11

This figure illustrates a modiiieation of the multistable circuit of Fig. 1, including a step function impedance network connected in a stage which is stable when the network impedance is high, and unstable when it is low. This modification includes a PNP junction transistor having an emitter electrode 90e, a base electrode 90b and a collector electrode 90C, and an NPN junction transistor 91 having an emitter electrode 91e, a base electrode 91b, and a collector electrode 91e. A step function impedance network 92 is connected between a terminal 94 connected to the emitter 90e and the positive terminal of a load battery 93, whose negative terminal is grounded.

The step function impedance load 92 differs `from the step function impedance 4 of Fig. 1 in that the polarities of the diodes are reversed. Note also that the polarity of battery 93 is reversed from that of battery 14 in Fig. 1.

The step function impedance 92 is shown as having two diode branches, and a resistor 97 connected between emitter 90e and positive terminal of battery 93. Each branch comprises a resistor 98, and a pair of oppositely poled diodes 99 and 100 having a common junction 101. The resistor 98 in each case is connected between the common junction 101 and the positive terminal of battery 93. Each of these branches includes a biasing battery, respectively indicated by the reference numerals 102 and 103. These batteries have terminal potentials differing from each other in steps, in a manner similarto the batteries;12, 17, 20 and 22 of Fig. 1.

Collector 90C is connected directly to` base 9125 and also through a load resistor 106 and a battery 107 to y so that The circuit of Fig. 11 dilfers from the circuit of Figs. l and 4 principally in that the stable regions of the load line are the high resistance regions of that line, whereas the unstable regions are the low resistance regions. In this respect, the operation of the circuit of Fig. ll is the Vopposite of the operation of the circuits of Figs. l and 4.

age to the ratio of the input voltage is greater than l,

the circuit is unstable. If the ratio is less than l, the circuit is stable.

The current I1 flowing from battery 93 through the load 92 to emitter 90e may be expressed as follows:

E1-E0 Ro Where E1 is the potential at the positive terminal of battery 93, E is the potential at the base 90b (assumed equal to potential at emitter 90e), and R0 is the impedance of network 92.

The potential E4 at the collector 90e may be expressed in terms of the potential E2 at the positive terminal of battery 107 and the potential drop` across resistor 106:

E4= E24-[1Km (21) Substituting (20) in (2l) E.=-E.+(-E-?olem 22) The current ow I2 through the emitter 91e may be expressed in terms of the potential drop across resistor 108 and the resistance of that resistor as follows:

E4-E'3 I 23 2 Rm t Where E3 is the potential of the negative terminal of battery 109.

Substituting (22) in (23), we get:

-E2 (E1*Eo) *E3 12- R108 R0Rl08 R106 R108 The feedback potential E may be expressed in terms of the potential E6 of battery 96 and the potential drop across resistor 111, as follows:

E5=Es2R111 (25) Substituting (24) in (25), we get:

EZRlll ElRlUGRlll EURlORlll E3R111 E' =E 26 5 T Rm Roem. Roem R10..

Diferentiating (26) with respect to the input potential E0, we get:

'YES RiuaRiit 7110 Roem i From (27) it follows that the circuit is unstable if R0 is less than is greater than l, and that the circuit is stable if R0 is greater than R108 so that fr 'YEO is less than 1.

FIG. 12

This figure illustrates still another circuit configuration which may be used with a step function impedance load in a manner generally similar to Fig. l1. This circuit includes -a PNP junction Vtransistor 113, having an emitter electrode 113e, a base electrode 113b, and a collector electrode 113C, and a PNP junction transistor 114, having an emitter electrode 114e, a base electrode 114b and a collector electrode 114C.

Emitter 113e is connected to a terminal 94 which may be the same as terminal 94 of Fig. 1l and may be connected to the same step function impedance means 92. Collector electrode 113e is connected through a load reistor 115 -and a battery 116 to ground. Collector 113e is also connected directly to base 114b. Emitter 114e is connected through a resistor 117 to ground. Collector 114C is connected through a load transistor 118 and a battery 119 to ground and to a loa-d branch including in series resistors 120 and 121 and a battery 122. The common junction 123 of resistors 120 and 121 is connected through a feed-back line 124 to base 113b.

FIG. 13

This figure illustrates graphically the operation of the circuit of Fig. 12. It shows a family of volt ampere characteristics for the emitter of transistor 113 of Fig. l2, for different values of base potential Eb. The various parameters involved are identified in the schematic diagram at the right-hand side of Fig. 13. On this family of characteristics there is superimposed a step function load line generally indicated by the reference numeral 125, and consisting of alternating low and high impedance regions H, I, J, K, L.

Consider the circuit of Fig. l2, when the potential of emitter 113e is at its most positive Value, which is determined by the intersection of region L of load line 125 with the current axis. The load on emitter 90e is then the resistance of resistor 97.

Considering the rst of the branch circuits in the step function impedance means 92, at this time, the anode of diode 100, at junction 101 is connected through resistor 98 to the positive terminal of battery 93. The cathode of diode 100 is, for example, at the potential of the negative terminal of battery 102. Diode 100 is therefore forwardly biased, and junction 101 is substantially the potential of the negative terminal of battery 102. The cathode of diode 99 is at the potential of emitter 90e, which is at this point somewhat more positive than the negative terminal of battery 102. Diode 99 is therefore reversely biased, and the only load on emitter 90e is resistor 97. As the potential of emitter 90e changes in a negative direction, it becomes equal to the potential of the negative terminal of battery 102, whereupon diode 99 becomes forwardly biased and the first resistor 98 is added as a load to the emitter 90e. This change occurs during the unstable region K of load line 125, and shifts the operating point of the circuit to the stable region I. As the emitter potential 90e becomes more negative, it passes at region I the potential of the battery 103. At that potential, another load resistor 98 is added, in parallel with the resistor 97, and the circuit operates in the stable region H.

FIG. 14

This figurel is a modification of Fig. 1, in which all the potentials are supplied from a single battery 126,. This circuit thereby avoids errors which might be encountered in the circuit of Fig. l due to the unequal changes of the various battery potentials with time.

Those circuit elements in Fig. 14 which correspond to their counterparts in Fig. 1 have been given the same reference numerals and will not be further described.

The battery 126 has connected across it a voltage divider including in series 8 resistors, numbered consecutively from 127 to 134. The common terminal of resistors 133 and 134 is grounded.

The step function impedance of this figure has an additional branch circuit as compared to that of Fig. 1, such additional branch circuit including diodes 135 and 136 oppositely poled with respect to a common junction 137, and a resistor 138.

An arrangement is shown for using the circuit of Fig. 14 as a decade counter. For this purpose, the input pulses to be counted are applied at an input terminal 139 from which they pass to a binary trigger circuit 14), which may, for example, be of the type described in the copending application of Robert A. Henle et al., Serial No. 459,381, filed September 30, 1954. This trigger circuit produces an output pulse for each two input pulses. These output pulses are transmitted to an input terminal 141 connected to a wire 142 which leads through capacitor 33 to the base 3b of the input gate of transistor 3. A reset gate is provided including a capacitor 143 and a diode 144 connected in series between wire 10 and wire 142, and a resistor 145 connected between the emitter 2e and common junction of diode 144 and capacitor 143.

A series of ten input signals at input terminal 139 will produce tive input signals at terminal 141 which in turn will shift the transistor 1 through its ve stable states.

On each input pulse, the binary trigger 140 shifts from one of its stable states to the other. In the arrangement illustrated, it will produce a positive going output signal on each odd numbered input pulse and a negative going signal on each even numbered input pulse. The input gate including transistor 3 responds only to negative going input signals.

Starting from the zero count condition of the transistor 1, the first negative input signal is received at base 3b at a time T2 when the negative going edge of the second input signal reaches input terminal 139. The transistor 1 advances through its ve stable states at the negative going end of each even numbered input signal. On the eighth input signal, the potential of emitter 2e is sufciently positive to bias the diode 144 forwardly, so that when the tenth input signal is received, the negative going signal at terminal 141 is transmitted through diode 144 and capacitor 143 and is effective to swing the emitter negatively, by cutting olf transistor 1 and resetting tbe collector 1c at its most negative or zero count potcntial.

FIGS. 15 AND 16 This circuit illustrates a multistable circuit generally similar to that of Fig. 1, using vacuum tubes as translating devices instead of transistors. The circuit` includes a p iode 146 connected in a grounded grid amplifier stage and triode 147 connected in a cathode follower stage. A step function impedance network 148 is connected as a load to the anode 146m of pentode 146.

The pentode 146 has a control grid 149 connected through a battery 151i to ground. The other grids of the pentode are connected in a conventional manner. The anode 1466i of pentode 146 is connected through a wire 151 to the control electrode 152 of triode 147. The cathode of triode 147 is connected through tWo series resistors 153 and 154 to ground. The anode of triode 147 is connected to the positive terminal of a battery 155, whose negative terminal is grounded. The cathode of pentode 149 is connected through a wire 17S to the common terminal 179 of resistorsl53 and 154.

The step function impedance network 148 includes live branches. One branch includes a diode 156 and a battery 157. A second branch includes oppositely poled diodes 158 and 159 having a common junction 160, and a resistor 161 connected between that junction and a positive terminal of battery 162. A battery 167 is connected between diode 159 and ground.

A third branch of the network 148 includes oppositely poled diodes 163 and 164 having a common junction 165, and a resistor 166 connected between the junction 165 and the positive terminal of battery 162. This branch also includes a battery 168 connected between diode 164 and ground. A fourth branch of the network 148 includes oppositely poled diodes 169 and 171B having a common junction 171, and a resistor 172 connected between junction 171 and the positive terminal of battery 162. A battery 173 is connected between diode 170 and ground.

The lifth branch of network 148 includes a junction 174, a diode and a battery 176 connected in series between junction 174 and ground, and a resistor 177 connected between junction 174 and the positive terminal of battery 162.

The batteries 157, 167, 168, 173 and 176 have progressively larger potentials, and battery 162 has a potential substantially greater than any of the others.

The operation of the circuit of Fig. 15 may best be understood by reference to the graphical illustration of Fig. 16. Fig. 16 shows a family of output characteristics of the pentode 146 for different values of the cathode current IC. In Fig. 16, the ordinates are anode currents Ip and the abscissae are anode potentials Vp. On this family of characteristics is superimposed a load line determined by the impedance of the step function network 148.

The diode 175 and battery 176 of Fig. l5 serve as a clamp to limit the maximum positive potential of anode 14651. If the potential of anode 146a tends to go higher than the potential of the positive terminal of battery 176, then diode 175 becomes biased forwardly, and prevents such a rise in the anode potential. This particular value of anode potential is indicated at V176 on Fig. 10.

As the potential of anode 146:1 decreases from this maximum value, the bias across diode 175 becomes reversed. During that reversal, the circuit operates in the stable region R. After the reversal is completed, the resistor 177 is effectively connected as a load to the anode 146a, and the circuit operates in the unstable region S.

Consider now the conditions in the fourth branch of the network 148, which branch includes the diodes 169 and 170. Junction 171 is connected through resistor 172 to the positive terminal of battery 162, which is substantially higher than the potential of battery 173. Diode 170 is therefore biased forwardly, with the result that junction 171 is substantially at the potential of the positive terminal of battery 173. Wire 151 is at this time more positive than this potential, so that diode 169 is reversely biased, and this branch of the network is not effective as a load on the anode 146a.

lf the potential of anode 146e and wire 151 decreases, further, then at some region such as the stable region T of the load line 180, the bias across diode 169 reverses, whereupon resistor 172 is connected as a load to the anode 146g, the circuit then operates in the unstable region U.

In an analogous manner a continued decrease in the potential will cause the circuitr to shift through the regions V, W, X, Y and Z of load line 180.

FIGS. 17 AND 18 This ligure illustrates a modification of the circuit of Fig. 1, including a novel type of step function impedance network, generally indicated'by the reference character 181, The network 181 employs silicon PN junction alloy diodes of the type described by G. L. Pearson and 181. The network 181 employs silicon PN junction Alloy Diodes, which appeared in vol. 40, No. 11 of the Proceedings of the Institute of Radio Engineers Vfor November 1952, pages 1348 to 1351. Such diodes yhave a peculiar volt/ampere characteristic. Most crystal diodes, for example, germanium diodes, have a low impedance in one direction termed'the forward direction and a high impedance rto the flow of current in the reverse direction. In this silicon junction alloy diode the high impedance in the reverse direction persists only until the reverse potential applied exceeds a certain value commonly referred to Vas the Zener voltage or Zener potential. When the reverse potential exceeds this value, the impedance of the diode again drops to a very low value, being as vlow or lower than the forward impedance and in many cases being Ysubstantially zero.

In the network 181 there are connected in series between collector 1c and base 2b, three of these silicon junction diodes, numbered respectively 182, 183 and 184.

Another silicon junction diode 185 is connected betweenv diodes 183 and 184. A fourth load resistor '194 is connected between the negative terminal of battery 188 and thecomm'on junction 195 between diode 184 and base 2b.

The several diodes 182, `183, 184 and 185 all 'havethe The operation of the circuit lof Fig. 17 may be summarized in the following table:

same Zener potential.

Table I Region 182 183 184 185 Zener. Zener Zener.- Zener Reverse -.-do .;do Do. Forwar -.dodo Do. Reverse--. -..do Do. d Forward.. ---do-- Do. do Reverse-.. Do. .-.do Forward.` Do.

do do Reverse. ...do do Forward.

When any of the diodes 182, 183, 184vand 185 `is forwardly biased or is reversely biased beyond its Zener potential, then its impedance is so small as to be negligible. vIn the region 196a 'of Fig. 18, the potential of collector 1c is suiciently Alow that all the diodes are reversely :biased beyond their Zener potential. `As the potential of collector 1c increases in a ,positive sense, thepotential across diode 182 decreases until it enters its reverse bias region. The load line 196 in Fig. 18 vthen enters the region 196b. This is an unstable region and the circuit passes through it rquickly to region' 196e, in which diode 182 becomes forwardly biased and the potential across it again drops to zero. This process is repeated for each of the diodes 182, 183, 184, as indicated by the table above. With regard to the diode. 185, its

cathode is at a xed negative potential of 1 volt and it.4

does not become positively biased until thecollector 1c swings more positive than -1 volt.

FIG. 19

This figure illustrates a multistable circuitsimilar to Point contact transistors such as transistor 197 Ahave avv ,30 tery 188 and the common junction 19.34 between silicon Y 18 current amplicationgreater than l. Consequently, a single transistor can provide sufficient output current for the necessary feedback. .Conventional junction :transistors such as the transistor .1 .of Eig. 1 have acurrent amplification factor lof approximately 1. Consequently, in view of thatlimitation, ,itisnecessary when using such transistors to use a second transistoras Yan amplienfor the feedback asin the circuitv of Fig. 1.

Any other equivalent translating Ydevicehaving suicient high amplification characteristics may be used to provide amultistable circuit.

The load resistors 5 and,.6 and the .battery 7 :may be the same in Fig. 19'as they areinFig. 1. The-step function impedance networkis indicated diagramn'latically at 198. The values of the circuit parameters in the circuit of Fig. 19 will have to be selected to match the impedance characteristics of the particular point .contact transistor being used. `For that reason, since presentppoint contact transistors do not have readily reproducible characteristics, itis presently preferred to use a two-stage amplifier circuit with 'junction transistors, as in Fig. 1, rather than the simpler circuit of Fig. 1'9.

While the transistors in the circuit illustrated are1 PNP junction transistors, it will be readily understoodv that NPN transistors can be used alternatively, providing that all the polaritiesof the batteries are reversed, ,and other changes made in accordance with principles well understood in the art. The following table showsby way of example particular values for the potentials of the various batteries and for the impedances of the various `resistors and capacitors, in circuits which have been operated successfully. In some cases, the valuesare alsoshowninthe-drawing. VThese values are also'set forth by vway of *ex-ampleonly, and "the invention is not limited to-them nor to any of'them. 5 The diodes are considered to have 4substantially-no impedance in their forward direction and 4substantially infinite ji111- pedance in the reverse direction.- Y Y Y Table Il FIGS. 1 AND 2 Resistor 5 -l500-ohms. Resistor 6 2000 ohms. Battery 7 15 volts. Battery 8 12 volts. Battery 12 10 volts, Resistor 13 51K ohms. Battery 14 100 volts. Battery 17 7 volts. Battery 20 4,volts. Y Battery 22 l volt. Resistor 23 51K ohms. Resistor '25 ,5 1K ohms. Resistor 26 1.5K ohms. Resistor 26a Resistor 27 510 ohms. Resistor 27a Resistor 28 7.5K ohms. Resistor v28a Resistor 30 1K ohm. Capacitor 32 .01 mf.` Capacitor 33 1000 mmf. Resistor 37 3K ohms; Battery 38 .'4 volts.` Battery 53 15 volts. Resistor 54 1'3 ohms; Resistor S5 13 ohms. Resistor 56 '13 ohms. Resistor 57 13 ohms. Resistor 58 13 ohms.' Resistor 59 '13 ohms. Resistor 60 ."13 ohms." Resistor 61 13 ohms. Resistor 62 13 ohms.

Resistor 63 9 ohms.-

19 Table II-Continued Resistor 66 300K ohms. Resistor 70 300K-330K ohms. Resistor 72 1K ohm. Capacitor 74 1000 mmf. Resistor 76 3K ohms. Battery 77 12 volts. Capacitor 78 .01 mf. Battery 80 5 volts. Resistor 83 200K ohms. vCapacitor 85 400 mmf. Capacitor 86 60 mmf. Battery 89 5 volts.

FIG. 4

Resistor 1650 ohms. Resistor 6 5.1K ohms. Battery 7 50 volts. Battery 8 15 volts. Battery 14 300 volts. Resistor 26 1.5K ohms. Resistor 26a 1.5K ohms. Resistor 27 510 ohms. Resistor 27a 510 ohms. Resistor 28 7.5K ohms. Resistor 28a 68K ohms. Resistor 30 1K ohm. Capacitor 32 .0l mf.

FIG. 11

Battery 93 70 volts. Battery 96 2.5 volts. Resistor 97 142K ohms. Resistor 98 35K ohms. Battery 102 1 volt.

Battery 103 3 volts. Resistor 106 1K ohms. Battery 107 10 volts. Resistor 108 3K ohms. Battery 109 12 volts. Resistor 111 2K ohms.

FIG. 12

Resistor 115 1K ohm. Battery 116 1() volts. Resistor 117 2K ohms. Resistor 118 3.3K ohms. Battery 119 72 volts. Resistor 120 1K ohm. Resistor 121 5.1K ohms. Battery 122 70 volts.

FIG. 14

Resistor 5 1.4K ohms. Resistor 6 43K ohms. Resistor 26 15K ohms. Resistor 27 510 ohms. Resistor 28 33K ohms. Resistor 30 1K ohm. Capacitor 32 .01 mf. Capacitor 33 1000 mfd. Battery 126 200 volts. Resistor 127 3.4K ohms. Resistor 128 10 ohms. Resistor 129 30 ohms. Resistor 130 39 ohms. Resistor 131 47 ohms. Resistor 132 47 ohms. Resistor 133 10 ohms. Resistor 134 610 ohms. Resistor 138 120K ohms. Capacitor 143 .005 mfd.

Resistor 145 5.1K ohms.

FIG. 15

Tube 146 Tube 6AC7. Tube 147 1/2 tube 12 AV7. Battery 150 150 volts. Resistor 153 3.7K ohms. Resistor 154 10.5K ohms. Battery 155 200 volts. Battery 157 35 volts. Resistor 161 140K ohms. Battery 162 400 volts. Resistor 166 170K ohms. Battery 167 45 volts. Battery 168 55 volts. Resistor 172 140K ohms. Battery 173 65 volts. Battery 176 75 volts. Resistor 177 230K ohms.

FIG. 17

Diode 182 Zener voltage=3 volts. Diode 183 Zener voltage=3 volts. Diode 184 Zener voltage=3 volts. Diode 185 Zener voltage=3 volts. Battery 186 1 volt. Resistor 187 51K ohms. Resistor 190 51K ohms. Resistor 192 51K ohms. Resistor 194 51K ohms. Battery 188 100 volts.

What is claimed is:

1. A counter circuit comprising a multistable stage including a first translating device having an output electrode and an input electrode, a step function impedance network connected to said output electrode as a load, feedback means connected between said output electrode and said input electrode, said translating device, said network and said feedback means cooperating to establish said stage in any one of a series of stable states defined by predetermined output electrode potentials, the several states in the series being separated by predetermined substantially equal potential increments, within which increments the stage is unstable, and input gate means for stepping said stage through said series of states, comprising a voltage divider connected to said multistable stage and effective at each state of said stage to develop at a junction in said divider a potential substantially equal to the potential derning a next adjacent stable state in the series, a second translating device connected between said junction and the output electrode of said rst translating device, means biasing said second translating device to a high impedance condition, and means for supplying to said second translating device a series of input pulses separated in time, each having a polarity and magnitude effective to switch said second device to a low impedance condition, said second translating device being thereupon effective to transfersaid junction potential to said output electrode of said rst device, thereby driving said stage from one stable state in said series to an adjacent one, so that the number of states through which the stage passes is a count of the number of input pulses.

2. A counter circuit as defined in claim 1, in which said voltage divider is elective to develop at said junction a potential defining the next higher potential state in the series, so that successive input pulses drive the multistable stage successively to states of increasing potential.

3. A counter circuit as defined in claim 2, including an output gate for producing an output signal when the multistable stage reaches its highest potential state, said output gate comprising a pair of output terminals, a source of electrical energy, a resistor connected in series with said source between said pair of output terminals, and a diode connected between one of said terminals and a point on said multistable stage subject to a potential varying with the state of said stage, means connecting the other of said output terminals to a common junction with said multistable stage, said source having-apolarty and potential effective to bias said diode reversely except when the potential at said point corresponds to that of the highest stable state of the multistable stage, said stage being then eective to transmit a current through said diode and through said resistor and thereby to' vary the potential of said one output terminal, y

4. A counter circuit as defined in claim 3 including reset means effective yon the next input pulse after the stage reaches its highest potential state to reset the stage at its lowest potential state, said reset means comprising a capacitor and a diode connected in series between the input electrode of said first translating device `and said input pulse supply means, and a connection between the common terminal of said capacitor and diode and va point in said multistable stage having a potential effective to bias said diode reversely except at the highest stable state of the multistable stage.

5. A counter circuit comprising a multistable stage including a first translating device having an output elecfrode and an input electrode, a step function impedance network connected to said output electrode .as a load, feedback means connected between said output electrode and said input electrode; said translating device, said network and said feedback means cooperating to establish said stage in any one of a series of stable states defined by predetermined potentials at one electrode of said device, the several states in the series being separated by predetermined, substantially equal, potential increments at said one electrode within which increments the stage is unstable, and input gate means for stepping said stage through said series of states, one at a time, comprising a source of potential having a value fixed in relation to the value of one of said increments, and means including said source for supplying to one electrode of said device a potential substantially equal to the potential defining one of the states adjacent in the series to the existing state, thereby driving said stage from said existing state to said adjacent state.

6. A counter circuit as defined in claim 5, including manually operable means for resetting said multistable stage at its lowest potential state.

7. A counter circuit as defined in claim 5, in which said potential supplying means is effective to supply a potential defining the state of next lower potential to the existing state.

8. A counter circuit as defined in claim 7, including means for producing an output signal when said multistable stage reaches its lowest potential state.

9. A counter circuit as dened in claim 8, including means operable upon production of said output signal to reset said multistable stage to its highest potential state.

10. A multistable circuit comprising a first transistor having an input electrode and an output electrode, a step function impedance network connected to said output electrode as a load, feedback means connected between said output electrode and said input electrode comprising a second transistor, means directly conductively coupling an input electrode of said second transistor to the output electrode of the first transistor and resistive means coupling the output electrode of the second transistor to the input electrode of the first transistor, said first transistor, said network and said feedback means cooperating to establish said stage in any one of a series of stable states dened by predetermined output electrode potentials, the several states in the series being separated by predetermined, substantially equal, potential increments, within which increments the stage is unstable.

1l. A multistable circuit as defined in claim l0, including means connecting the base electrode of said first transistor to ground, and means connecting the collector electrode of the seco-nd transistor to ground.

12. A multistable circuit as defined in claim 10, in Which said first transistor is a PNP junction transistor,

having emitter, collector and` base electrodes, saidsecond transistor is `an NPN junction transistor havingV emitter, collector and base electrodes, means vdirectly conductively coupling the collector of the first transistor to the base of the second transistor, means directly conductively coupling the collector of the second transistor to the base of the first transistor, means connecting said step function impedance network to the emitter of the first transistor, and means connecting the emitter of the second transistor to ground.

13. A counter circuit comprising a multistable stage including a first transistor 'having an input electrode and an output electrode, a step function impedance network connected to said output electrode as a load, feedback means connected between said output electrode and said vinput electrode comprising a second transistor, means coupling an input electrode of said second transistor to the output electrode of the first transistor andv means coupling the output electrode of the second transistor to the input electrode of the first transistor; said first transistor, said network and said feedback means cooperating to establish said stage in any one of a series of stable states defined by predetermined output electrode potentials, the several states in the series being separated by predetermined, substantially equal, potential increments, within which Vincrements the stage is unstable, and input gate means for stepping said stage through said series of stable states, step by step, comprising a source of potential having a value fixed in relation to the value of one of said increments, and means including said source for supplying to said stage a potential substantially equal to the potential defining one of the states adjacent in the series to .the existing state, thereby driving said stage from said existing state to said adjacent state.

14. A counter circuit as defined in claim 13, in which said input gate means comprises a voltage divider connected to said multistable stage and effective at each state of said stage to develop at a junction in said divider a potential substantially equal to the potential defining a next adjacent stable state in the series, a third transistor connected between said junction and the output electrode of said first transistor, means biasing said third transistor to a high impedance condition, and means for supplying to said third transistor a series of input pulses separated in time, each having a polarity and magnitude effective to switch said third transistor to a low impedance condition, said third transistor being thereupon effective to transfer said junction potential to said output electrode of said rst transistor, thereby driving said stage from one stable state in said series to an adjacent one, so that the number of states through which the stage passes is a count of the number of input pulses.

15. A counter circuit comprising a multistable stage including a first transistor having an output electrode and an input electrode, a step function impedance network connected to said output electrode as a load, feedback means connected between said output electrode and said input electrode; said transistor, said network and said feedback means cooperating to overcome said bias and switch the second transistor on, said second transistor being thereupon effective to transfer said potential of said one junction to said point in said multistable stage, thereby driving said stage from one stable state in said series to an adjacent one, so that the ntunber of states through which the stage passes is a count of the number of input pulses.

16. A counter circuit is defined in claim l5, in which said input pulse supply means has a predetermined time constant, and including a capacitor connected to said voltage divider and effective to establish at said one junction a substantially longer time constant, so that each input pulse terminates before said one junction is driven to a new potential value by the stepping action initiated by that input pulse.

17. A counter circuit as defined in claim 5, in which aeoasoa i' as said feedback means comprises a constant current source, means directly connecting said constant current source to said input electrode, and means including a resistor connecting said constant current source to said output electrode.

18. A counter circuit for counting a series of input signal pulses comprising a binary trigger circuit having an input connected to receive said pulses and an output and adapted to produce a pulse at said output upon receipt of every second input pulse of the series; a multistable stage including a first translating device having an output electrode and an input electrode, a step function impedance network connected to said output electrode as a load, feedback means connected between said output electrode and said input electrode; said translating device, said network and said feedback means cooperating to establish said stage in any one of a series of stable states defined by predetermined potentials at one electrode of Asaid device, the several states in the series being separated by predetermined, substantially equal, potential increments of said one electrode within which increments the stage is unstable, and input gate means for stepping said stage through said series of states, one at a time, comprising a source of potential having a value fixed in relation to the value of one of said increments, and means including said source for supplying to one electrode of said device a potential substantially equal to the poten- 24' tial defining one of the states adjacent in the series to the existing state, thereby driving said stage from said existing state to said adjacent state, and means connecting said multistable stage and said binary trigger circuit in cascade.

19. A counter circuit as defined in claim 18, in which said multistable stage has a series of five stable states determined by said different biasing potentials, and is shifted from one state to the next by an input pulse, and includes means to produce an output signal pulse whenever it reaches the last state of the series, and means to reset the multistable stage at the first state of the series when said output signal is produced, said cascaded stage and circuit cooperating to produce an output signal for each ten input signal pulses.

References Cited in the file of this patent UNITED STATES PATENTS 2,486,391 Cunningham Nov. 1, 1949 2,647,238 Bailey July 28, 1953 2,652,460 Wallace Sept. 15, 1953 2,701,303 Wells Feb. 1, 1955 2,714,702 Shockley Aug. 2, 1955 2,743,359 Sayre Apr. 24, 1956 2,773,980 Oliver Dec. 11, 1956 2,810,072 Amatniek Oct. 15, 1957 

